Electronics and Communications Technology

VLSI Architecture for Signal, Speech, and Image Processing
Advances, Challenges, and Potential

Editors: Durgesh Nandan, PhD
Basant Kumar Mohanty, PhD
Sanjeev Kumar, PhD
Rajeev Kumar Arya, PhD

VLSI Architecture for Signal, Speech, and Image Processing

Published. Available now.
Pub Date: November 2022
Hardback Price: see ordering info
Hard ISBN: 9781774637302
E-Book ISBN: 9781003277538
Pages: 342PP w/index
Binding Type: hardback / ebook
Notes: 174 b/w illustrations

This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate.

Knowledge of VLSI is necessary for understanding today’s contemporary hardware prospects of engineering. It is the process of creating an integrated circuit by combining millions of MOS transistors onto a single chip that is needed for handheld portable battery-operated devices that require efficient, errorless, and low-power arithmetic operation. VLSI plays a most important role in the performance of digital systems, digital signal processing (DSP), image processing applications, hardware security, quantum computing, etc. Especially in DSP systems, the algorithms of VLSI have a number of interesting characteristics that can be exploited in the design of the arithmetic circuits so that they can be implemented more efficiently in terms of computation time, chip area, and power consumption.

This volume, VLSI Architecture for Signal, Speech, and Image Processing, provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations. It covers how computer arithmetic contributes to the era of quantum computing, hardware security, image processing, biomedical engineering, artificial intelligence, neural networks, and stochastic computing.

Prepared by leading researchers in the field of computer arithmetic architecture, the state-of-the-art information presented here helps to provide a comprehensive understanding of VLSI for students, faculty, and researchers in computer science, computer engineering, and electrical and electronics engineering. It may be used as a textbook for courses on VLSI as well as a reference book.

CONTENTS:

Preface

1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform VLSI Architecture
C. S. N. Koushik, Abhishek Choubey, Shruti Bhargava Choubey, and D. Naresh

2. Execution of Lifting-Scheme Discrete Wavelet Transform by Canonical Signed Digit Multiplier
Gundugonti Kishore Kumar and Narayanam Balaji

3. Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in the Field of 2D DWT Architecture
Gundugonti Kishore Kumar and Narayanam Balaji

4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra Low Supply Voltages Using FinFET with 20nm Technology
Vallabhuni Vijay, Pittala Chandra Shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Merugu Rachana, and Nakka Nikhil

5. Design and Statistical Analysis of Strong Arbiter PUFs for Device Authentication and Identification
Kurra Anil Kumar and Usha Rani Nelakuditi

6. An Impact of Aging on Arbiter Physical Unclonable Functions
Kurra Anil Kumar and Usha Rani Nelakuditi

7. Advanced Power Management Methodology for SoCs Using UPF
Usha Rani Nelakuditi, Naveen Kumar Challa, and K. Anil Kumar

8. Architecture Design: Network-on-Chip
N. Ashok Kumar, A. Kavitha, P. Venkatramana, and Durgesh Nandan

9. Routing Strategy: Network-on-Chip Architectures
N. Ashok Kumar, S. Vishnu Priyan, P. Venkatramana, and Durgesh Nandan

10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems
Roopa R. Kulkarni and S. Y. Kulkarni

11. Optimization of SoC Sub-Circuits Using Mathematical Modeling
Magnanil Goswami

12. An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits
Birinderjit Singh Kalyan, Harpreet Kaur, Khushboo Pachori, and Balwinder Singh

13. Design and Performance Analysis of Digitally Controlled DC-DC Converter
Subhransu Padhee, Madhusmita Mohanty, and Ambarish Panda

Index


About the Authors / Editors:
Editors: Durgesh Nandan, PhD
Research Mentor and Account Manager, Accendere Knowledge Management Services Pvt. Ltd. (subsidiary of CL Educate Ltd)

Durgesh Nandan, PhD, is a Research Mentor and Account Manager at Accendere Knowledge Management Services Pvt. Ltd. (100% subsidiary of CL Educate Ltd). He formerly served as Assistant Professor and Head of Department in the Department of Electronics and Communication Engineering, IASSCOM Fortune Institutes of Technology, India, as well as a guest faculty under the Special Manpower Development Program for Chips to System Design (SMDP-C2SD) in the Department of Electronics & Communication Engineering, NIT, Patna, India. He is session chair, technical program committee chair, reviewer, and member of more than 50 national and international conferences. He is the author or a co-author of more than 90 papers. He is inventor or co-inventor of a published Indian patent and six Indian patents in process of filing. He is the author or a co-author of two books. His research interests include computer arithmetic, VLSI architecture for signal processing applications, speech processing, hardware architecture of real time big data/AI applications, and Internet of Things. He founded the prestigious JSS Fellowship for 2014 to 2018 by Jay-Prakash Sewa Sasthan. He also received a “Young Personality of the Year Award (under 40 years)” in 2019 by the International Academic and Research Excellence Awards (IARE–2019). He also awarded at “I2OR Preeminent Researcher Award 2019” in 2019 for remarkable contribution in the field of VLSI and DSP by the International Institute of Organized Research.

Dr. Nandan earned a PhD from the Department of Electronics & Communication Engineering, Jaypee University of Engineering and Technology, Guna, Madhya Pradesh, India, with the specialization in VLSI. His MTech, with specialization in Microelectronics & VLSI Design, and his BS (Engineering) were awarded by E.C.E from Rajeev Gandhi Technical University, Madhya Pradesh, India.

Basant Kumar Mohanty, PhD
Professor and Associate Dean (Research), Mukesh Patel School of Technology, Management and Engineering, Narsee Moonjee Institute of Management Studies, Maharashtra, India

Basant Kumar Mohanty, PhD, is a Professor and Associate Dean (Research) at the Mukesh Patel School of Technology, Management and Engineering, Shirpur Campus, at the Narsee Moonjee Institute of Management Studies (Deemed-to be University), Mumbai, Maharashtra, India. He is also an Associate Editor for the Journal of Circuits, Systems, and Signal Processing, a senior member of IEEE Circuits and System Society, and a life-time member of the Institution of Electronics and Telecommunication Engineering, New Delhi, India. He formerly has worked with various institutions during his career, starting his professional teaching career at Odisha Education Service, Class-II Gazetted, and he joined SKCG (Autonomous) College, Paralakhemundi, Odisha. Later he moved on to join BITS Pilani- Rajasthan, Mody University of Science and Engineering-Rajasthan, Jaypee University of Engineering and Technology, Guna-Madhya Pradesh, India. He has also been associated with Qatar University and the School of Computer Engineering, Nanyang Technological University, Singapore, for postdoctoral research. His research interests include design and implementation of reconfigurable architectures for domain-specific signal processing applications, approximate computation, stochastic computation, and compressed sensing. He has contributed more than 60 technical papers to various reputed journals and conference proceedings, which includes over 34 SCI journal publications with over 17 IEEE Transaction papers. He has research collaboration with faculties of top technical universities within and outside India.

Sanjeev Kumar, PhD
Research Mentor, CL Educate Ltd., India

Sanjeev Kumar, PhD, is working as a Research Mentor in CL Educate Ltd., India. He served as Assistant Professor in the Department of Electronics and Communication Engineering, TIT Group of Institutes, India, as well as Assistant Professor in the Electronics and Communication Engineering Department at the Oriental Group of Institutes, Bhopal, India. He had a six-month research experience as a project fellow at the Division of MMIC in the Defence Research and Development Organisation, Delhi, India. He is technical program chair, reviewer, and member of more than 40 refereed national/international conferences. He is the author or a co-author of more than 65 papers, which were published in SCI, Scopus, and peer-reviewed international journals and conference proceedings. His research interests are in design and modeling of microstrip antennas, digital signal processing, metamaterials, and RF circuit design. Dr. Kumar earned his PhD in design and analysis of UWB and MIMO antenna systems for communication systems from Jaypee University of Engineering and Technology, Guna, India. He did his MTech degree with specialization in microwave-electronics at the University of Delhi, India, and his bachelor of engineering degree in electronics and communication engineering from Rajiv Gandhi Technical University, Bhopal, India. He founded the prestigious “JSS Fellowship” for 2014 to 2018 at Jayaprakash Sewa Sasthan, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India.

Rajeev Kumar Arya, PhD
Assistant Professor, Department of Electronics and Communication Engineering, National Institute of Technology, Patna, Bihar, India

Rajeev Kumar Arya, PhD, is currently an Assistant Professor with the Department of Electronics and Communication Engineering at the National Institute of Technology, Patna, India. He was formerly an Associate Professor in the Department of Electronics and Communication Engineering in CMR Engineering College, Hyderabad, India. His current research interests are in wireless communication, soft computing techniques, cognitive radio, signal processing, communication systems, and circuits design. He has published many articles in international journals and conferences and has received a best paper award at the International Conference on Communication Engineering and Technology (2019). He serves as a guest editor of the International Journal of Information Technology and Web Engineering (IJITWE) and the International Journal of Computational Systems Engineering and is a reviewer for IEEE Communication Letter and other journals. He is a member of the IEEE, ISRD and the International Association of Engineers. Dr. Arya received his degree in electronics and communication engineering from the Government Engineering College, Ujjain, (RGPV University, Bhopal), India and his master of technology in electronics and communication engineering from the Indian Institute of Technology, Dhanbad, India. He received his PhD degree in communication engineering from the Indian Institute of Technology, Roorkee, India. He has received a Ministry of Human Resource Development Scholarship (MHRD India) during his MTech and PhD work.




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