Electronics and Communications Technology

AAP Advances in Materials, Manufacturing and Computational Intelligence Techniques

Modern Nanoscale Field-Effect Transistors
Fundamentals, Challenges, and Future Technological Innovations

Editors: Dr. Ashish Kumar Singh
Dr. Kaushal Kumar
Dr. Ramesh Kumar

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Modern Nanoscale Field-Effect Transistors

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Series: AAP Advances in Materials, Manufacturing and Computational Intelligence Techniques

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The scope of the book encompasses the simulations and mathematical modeling techniques for heterojunction nanoscale FETs, laying a theoretical foundation for high-performance semiconductor devices. It comprehensively discusses the design and performance investigation of heterojunction nanoscale field effect transistors (FETs). In addition to materials, it explores novel materials, innovative design methodologies, and analytical strategies for electronic devices used in wireless communication systems. It is tailored for engineers, researchers, and students seeking to deepen their understanding of the rapidly advancing wireless technology sector. It also covers extensive analysis of TFET technology addresses design strategies, performance benchmarks, and its promise in low-power future devices, including junctionless designs. Furthermore, it discussed design strategies, performance evaluation, and prospects for next-generation devices and included the fabrication challenges and sustainability considerations of nanoscale devices. Highlights the influence of advanced materials like SiGe, InAs, and GaAs on device scaling, speed, and energy efficiency, this book serves as both a foundational reference and a forward-looking guide, offering critical insights into the simulation, modeling, and application of FETs devices that empower next-generation electronics and VLSI technologies.

Coverage
Submission of book chapters should be focused on the following key highlights:

Chapter 1. Design and performance investigation of heterojunction Nanoscale Field Effect Transistors (FETs): Simulation and mathematical Modeling (Material heterogeneity for enhanced electrostatic control, reduced leakage, and improved carrier injection in ultra-scaled devices suitable for low-power and high-speed electronic applications)

Chapter 2. In-Depth Analysis of Tunnel Field-Effect Transistor Technologies: Design Strategies, Performance Evaluation, and Prospects for Next-Generation Devices (To investigate electrical performance metrics including ON-current, OFF-current, SS, DIBL, transconductance, and cutoff frequency of TFETs)

Chapter 3. Fabrication Challenges and Sustainability Considerations in the Transition Toward Eco-Friendly Physical Design in Semiconductor Manufacturing Applications (Focuses on addressing the critical fabrication challenges and integrating sustainability principles into the physical design and manufacturing processes of semiconductor devices)

Chapter 4. Comprehensive Characterization of Conventional Nanoscale Field-Effect Transistor (FET) Structures: Electrical, Thermal, and Performance Metrics (Focuses on evaluating FET’s electrical, thermal, and operational performance in scaled technology nodes (<10 nm) with aggressive scaling, understanding and optimizing these parameters is crucial for ensuring device reliability, energy efficiency, and integration feasibility)

Chapter 5. Material Engineering in Semiconductor FETs: Impact on Device Architecture, Performance, and Next-Generation Technology Nodes (Explores the pivotal role of material engineering in shaping the design, performance, and scalability of semiconductor field-effect transistors (FETs))

Chapter 6. Electrical Behavior and Performance Optimization of Nanoscale Single-Gate and Multi-Gate FET Devices for Advanced Semiconductor Applications (Investigates the electrical behavior, design trade-offs, and performance optimization of nanoscale single-gate and multi-gate FET architectures)

Chapter 7. Advanced Circuit Design and Simulation of Nanoscale FETs Using Cadence Tools: Insights into Device Scaling and Performance Metrics (The aim is to bridge the gap between device-level innovation and circuit-level implementation, focusing on the effects of device scaling on key analog, digital, and mixed-signal performance metrics)

Chapter 8. Detailed Compact Analysis of Nanoscale FETs for RF Circuit Design: Implications for Power, Speed, and Noise Performance (Addressing key metrics such as power consumption, operating frequency, gain, and noise performance)

Chapter 9 Exploring the Role of Semiconductor FETs in Optical Device Integration: Design Approaches and Application Potential (Investigates the integration of semiconductor field-effect transistors (FETs) with optical and optoelectronic devices, focusing on emerging opportunities in opto-FET design, electro-optical modulation, and photodetection)

Chapter 10. Design and Development of Semiconductor Field-Effect Transistors for Advanced Sensing Applications in Biomedical and Environmental Domains (Focuses on the design, modeling, and application of semiconductor field-effect transistors (FETs) for high-sensitivity sensing in biomedical and environmental monitoring)

Chapter 11. Bandgap and Gate Underlap Engineered SiGe/InAs/GaAs Junctionless TFET for Improved Wireless Applications (Explores the design, modeling, and performance optimization of a Junctionless Tunnel Field-Effect Transistor (JL-TFET) using bandgap-engineered heterostructures of SiGe, InAs, and GaAs, with an emphasis on gate underlap engineering)

Chapter 12. Impact of mole fraction of SiGe on the analog/RF performance of junctionless Tunnel Field effect Transistor (JLTFET) (Investigates the influence of varying the mole fraction of Silicon-Germanium (Si???Ge?) in the source region of Junctionless Tunnel Field-Effect Transistors (JL-TFETs) and its effect on analog and RF performance metrics)

Chapter 13. A Comparative Study of Power Consumption and Transistor Drive Current Characteristics in 6T and 9T SRAM Cell Architectures (Presents a comparative analysis of 6-transistor (6T) and 9-transistor (9T) Static Random Access Memory (SRAM) cell architectures, with a focus on power consumption, stability, and transistor drive current behavior)

Chapter 14. Harnessing Electron Spin for Innovation: A Comprehensive Overview of Spintronic Devices and Their Role in Shaping Future Technologies (This chapter offers a comprehensive exploration of spintronic devices, which utilize the intrinsic spin of electrons along with their charge for data storage and logic operation)

Chapter 15. Exploring GaSb/Si Type-II Heterojunction TFETs on Substrate for Dielectric Modulated Label-Free Biosensing: Device Physics and Application Prospects (This research investigates the design and operation of GaSb/Si-based Type-II heterojunction tunnel field-effect transistors (TFETs) integrated with dielectric modulation for use in label-free biosensing applications)

Chapter 16. Conclusion and Future Scope




Important Dates:
Abstract Submission (200 – 300 words) Deadline: September 25th, 2025
Notification of Acceptance: September 30th, 2025
Full Chapter (4,000 – 6,000 words) Submission Due: On or before November 20th, 2025

Submission procedure:
We invite researchers and practitioners to contribute original chapters to this book. Prospective authors are encouraged to submit a one-page chapter proposal or abstract outlining the proposed chapter’s content, objectives, and methodology by September 25th, 2025. Please include the chapter title and author details within the proposal. Authors will be notified regarding the acceptance of their proposals by September 30th, 2025. Accepted authors will be required to submit completed chapters of 15 to 20 pages by November 20th, 2025. All submitted chapters will undergo a rigorous peer-review process.

To submit your proposal or full-length chapter, please send a Word document attachment to editors: ashishkrsinghiitbhu@gmail.com, kaushaliit0608@gmail.com, rameshkumarmeena@gmail.com

Authors must refer to the following link for detailed guidelines for chapter preparation: http://www.appleacademicpress.com/publishwithus


Note: Authors submitting manuscripts to this book do not incur any publication fees. To ensure the originality and quality of the content, all submissions must be previously unpublished and not under consideration for publication in any other venue.


About the Authors / Editors:
Editors: Dr. Ashish Kumar Singh
Assistant Professor of Department Electronics and Communication Engineering, Graphic Era (Deemed to be University), 566/6, Bell Road, Society Area, Clement Town, Dehradun, Bharu Wala Grant, Uttarakhand 248002

Dr. Kaushal Kumar
Associate Professor of Department Electronics and Communication Engineering, Graphic Era (Deemed to be University), 566/6, Bell Road, Society Area, Clement Town, Dehradun, Bharu Wala Grant, Uttarakhand 248002

Dr. Ramesh Kumar
Assistant Professor, Department of DICE, Chitkara University, Chandigarh-Patiala National Highway (NH- 64 Village Jansla, Rajpura, Punjab 140401




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